The present invention relates to the efficient design of very-large-scale integrated (VLSI) circuits, and more particularly to a method for optimization of signal timing delays through LSI circuits by proper selection of circuit power levels.
The problem of designing LSI circuits within predefined timing constraints is well known, and can be simply stated as a problem of minimizing the power consumption of an LSI circuit subject to the timing constraints imposed upon the LSI circuit by virtue of its interconnection to other circuits. In any complex digital system, signals are transmitted and received by individual circuits, requiring interdependent timing relationships for proper and integrated operation. Such circuits function by detecting the presence or absence of signals at predetermined input terminals within a predetermined time "window", performing various predesigned logical combinations on the basis of these detected signals, and developing output signals for subsequent processing by other circuits. Systems are designed with complex interactions of such circuits, according to an overall timing scheme which ensures the proper timed interaction of all circuits.
In LSI circuit design, it has become the practice to formulate an overall LSI chip from the predetermined interconnection of a plurality of individual circuit cells. A typical LSI chip may have several thousand circuit cells constructed thereon, individual cells being constructed from a standardized manufacturing process which is simultaneously applied to develop the LSI chip. One or more standardized cells are interconnected to form various logic combinations, to perform specified logic functions, each of which may be identified as a logic block of some predetermined definition. Logic blocks have characteristically been designed with inherent power drive circuitry, and specifically with the capability of providing multiple levels of power drive capability.
The switching times of individual transistor circuits are known to be a function of the power applied to the circuit, and in the case of logic blocks it is advisable to provide the capability of multiple power drive levels to permit selection of an appropriate power level to achieve a predetermined system timing parameter.
Of course, it is possible to achieve the fastest signal transmission times by merely selecting the highest possible power level, but in a complex system having thousands of circuit interconnections it is neither necessary nor desirable to achieve the fastest possible individual circuit transmission times, for different logic blocks have different serial circuit interconnections and therefore inherently provide different signal delays from input to output. Further, merely assigning the highest possible power level to each circuit block for achieving maximum speed leads to unnecessary power consumption when such speed is unnecessary. Therefore, the problem is one of determining the minimum power requirements for a given combination of logic blocks consistent with the overall and interdependent timing requirements of those logic blocks.
Previous methods have been developed for determining the timing characteristics of a plurality of logic blocks, and to provide an indication of timing path delays between the blocks. U.S. Pat. No. 4,263,651, issued Apr. 21, 1981, shows a method for analyzing logic blocks arranged in predetermined circuit configurations to identify critical timing paths and to determine whether the path delays of such critical paths are too long or too short. This method enables individual logic blocks to be redesigned whenever critical paths are identified which are either too long or too short, in order to provide an overall system for reliable operation. Likewise, analytical power/timing techniques have been described for optimizing logic circuit designs, such as described in a paper entitled "Analytical Power/Timing Optimization Technique for Digital System", presented at the Fourteenth Design Automation Conference on June 20-22, 1977, in New Orleans, La., by A. E. Ruehli, P. K. Wolff, Sr., and G. Goertzel of the IBM Thomas J. Watson Research Center. This paper describes a method for logic gate delay assignment which achieves power minimization of digital logic while satisfying system timing, but which requires simplistic assumptions of the power/delay model in order to perform the analysis.
A further description of a design technique for circuits of this type is discussed in a paper entitled "Philo - a VLSI Design System", presented at the Nineteenth Design Automation Conference, June 14-16, 1982, Las Vegas, Nev., by the authors R. Donze, J. Sanders, M. Jenkins, G. Sporzynski, of the IBM Corporation. This paper describes a VLSI circuit design technique with which the present method is uniquely adaptable, and further describes a delay calculator/optimizer software program which functions by analyzing each logic block to determine its output load capacitance, calculating its circuit delay, comparing this delay to a delay goal and then selecting a higher power level if the original delay does not meet the goal. This technique assumes a worst-case delay goal for individual logic blocks, with no consideration of overall system timing constraints, merely setting forth a technique for achieving individual circuit block timing goals without necessarily considering the overall impact of a plurality of such logic blocks in a total system timing problem.
There is a need to provide a method for optimizing power consumption of individual logic blocks, consistent with overall system timing requirements and goals, wherein individual logic block power levels may be selected and adjusted for achieving overall system timing requirements. The present invention achieves this result, through application of the method described herein.